US3812475A - Data synchronizer - Google Patents

Abstract

A data processing system in which a plurality of data channels control the simultaneous exchange of data between many input/output devices, and a common shared storage. The channels automatically extract control instructions from storage and interpret them to independently carry out data transfers. Each data channel is initialized by the central processing unit (CPU) which causes a control word to be transferred from storage to the data channel where it is stored. The data channel utilizes the control word to start an input/output operation. The input/output operation is continued automatically by the channel which has means for retrieving subsequent control words from storage independent of the CPU. Data transfers between a data channel and the storage over a common storage bus are performed by a ''''cycle stealing'''' capability wherein execution of the CPU program may be delayed for one storage cycle, which cycle is utilized by the channel to store a word of data in the storage. Competing requests among data channels and the CPU are resolved by a priority circuit which grants storage access to the highest priority channel demanding access. The CPU is given the lowest priority. Since the channels direct the flow of information between I/O devices and main storage, they relieve the CPU of the task of communicating directly with the devices and permit data processing to proceed concurrently with I/O operations.

Description

United States Patent Christiansen et a1.

1 May 21, 1974 1 1 DATA SYNCHRONIZER [75] Inventors: Carl L. Christiansen; Lawrence E.

Kanter, both of Poughkeepsie; George R. Monroe, Wappingers Falls. all of NY.

[73] Assignee: International Business Machines Corporation, New York. NY.

[22] Filed: Dec. 26. 1957 [21] Appl. No: 705.447

[52] 0.8. CI. 340/1725 [51] Int. Cl. 60619/18 [58] Field of Search 235/61 PB. 61 MS, 157. 235/165, 166. 167

[56] References Cited UNITED STATES PATENTS 3.029.414 4/1962 Schrimpl 340/1725 3.142.043 7/1964 Schrimpf 340/1725 3.231.865 1/1966 Wilenitz 340/1725 3.234.517 2/1966 Herold et a1 340/1725 3.283.308 11/1966 Klein et a1. 340/1725 3.334.333 8/1967 Gunderson et a1. 2.604.262 7/1952 Phelps et all. 2.636.672 4/1953 Hamilton et a1. 340/1725 X 2.679.638 5/1954 Bensky et a1. 340/1725 2.767.908 10/1956 Thomas 340/1725 2.796.218 6/1957 Toolill et a1. 340/1725 2.805.283 9/1957 Stiles 178/2 2.960.683 11/1960 Gregory et a1 340/1725 FOREIGN PATENTS 0R APPLICATIONS 1.099.467 3/1955 France 340/1725 749.836 6/1956 Great Britain 340/1725 OTHER PU BLlCATlONS E.R.A. 24-Digit Parallel Computer with Magnetic Drum Memory (PX29136)." Eng. Research Assoc.

Inc. St. Paul. Minn.. 1949. pp. 4. 5. 7-22. 27-36.

Primary liraminerRaulfe B. Zache Attorney. Agent. or Firm-Hanifin & Jancin ABSTRACT A data processing system in which a plurality of data channels control the simultaneous exchange of data between many input/output devices. and a common shared storage. The channels automatically extract control instructions from storage and interpret them to independently carry out data transfers.

Each data channel is initialized by the central processing unit (CPU) which causes a control word to be transferred from storage to the data channel where it is stored. The data channel utilizes the control word to start an input/output operation. The input/output operation is continued automatically by the channel which has means for retrieving subsequent control words from storage independent of the CPU. Data transfers between a data channel and the storage over a common storage bus are performed by a cycle stealing" capability wherein execution of the CPU program may be delayed for one storage cycle. which cycle is utilized by the channel to store a word of data in the storage. Competing requests among data channels and the CPU are resolved by a priority circuit which grants storage access to the highest priority channel demanding access. The CPU is given the lowest priority.

Since the channels direct the flow of information between [/0 devices and main storage, they relieve the CPU of the task of communicating directly with the devices and permit data processing to proceed concurrently with 1/0 operations.

91 Claims. 506 Drawing Figures 10 1C is tat it time PATENTEBIAX 21 mm 38 121475 sum 01 or 409 FPUNCHED CARD CARD PRINTER READER PUNCH TAPE CHANNEL CONTROL A 4.20-1

UNIT ao-1A 1.20-1A CHANNEL CONSOLE 1 H T 1.ZQB-1 DATA TU TU TU TU SYNCHRONIZER 1 1l52-1A 1fi2-4A 152-5A 1.52M CENTRAL PROCESSING L1-10 REAL TIME DEVICE 154- MAGNETIC coRE STORAGE 1.12 TAPE co N T oL 'I 1' 1 TO PR|N TER MAGNETIC was DRUM TU TU TU TU L 130-2 STORAGE 132-151 152-48 152-58 CHANNEL T0 TCU C C 1.20-2 TOR LTIMEDEVICE EA 2 cHAgNEL FIG 1 .To TCU/ DATA SYNCHRONIZER 2 mPRmTERq' TCU CHAENEL mvmons MEAL 120-35 CARL L. cnmsnmseu TIME DEVICE w CHANNEL LAWRENCE E KANTER F 420-5 GEORGE R. MONROE l J 1.ZO-3F Mm BY W 21,.

SYNCHRONIZER a ATTORNEY PAIENTEDRAYZWM 3,812,475

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Claims (91)

1. A data processing system Operable by main instructions comprising, in combination, a storage device for providing a series of said main instructions and control instructions, a plurality of input-output devices independently operable in response to said control instructions, and multi-channel apparatus including a control device for each of said channels in tandem relationship with said storage device and said inputoutput devices, each of said channels having means to store a plurality of control instructions to be executed consecutively concerning input-output operation, and means for serially moving said control instructions through said channels upon execution of any one operation of said input-output device.

2. A data processing system comprising, in combination, a primary calculator, a plurality of control devices, each including secondary calculating apparatus units for the interpretation of main and control instructions, a shared storage device providing a common information source of data and data handling commands between said plurality of control devices and said primary calculator and the means for communicating said data and data handling commands, and means actuated in response to stimuli from said primary calculator to said storage device to provide initial main instructions to said control devices concerning the type of operation to be performed and the location in the shared storage device from which subsequent control instructions are extracted automatically by the control devices in response to operation of said secondary calculating apparatus.

3. A data processing system comprising, in combination, a device for serially providing address manifestations, an addressable storage device for the storage and transmission of data serially by word in response to said address manifestations, a plurality of input-output devices for receiving and transmitting said data, a plurality of control devices each independently operable in accordance with a separate program directly coupling said input-output devices and said storage device and each adaptable to store and to receive address manifestations and to transmit data, from and to corresponding locations of said storage device in a synchronous manner and to transmit information from and to said input-output devices in an asynchronous manner said control devices adapted to distribute signals representative of words of data serially to and from said storage device and adapted to transmit data signals in parallel, as among said input-output devices, to and from said input-output devices.

4. In a data handling system, apparatus comprising a plurality of selectively operable auxiliary storage devices adapted to receive and store information units in response to read and write signals, a shared storage device adapted to receive and store information units in response to read-in and read-out signals, and bilateral data transmission devices coupling said auxiliary storage devices and said shared storage device and operable in response to predetermined individual programs of control words for providing read and write signals serially to said shared storage device and for providing said read and write signals to said selectively operable auxiliary storage devices according to said predetermined programs.

5. In a data processing unit in combination with a primary storage device having individual information storage locations for receiving and transmitting information in response to read and write signals and a plurality of secondary storage devices individually operable to receive and transmit information in response to said read and write signals, data handling apparatus comprising at least two information transporting channels, each channel having execution means for controlling the passage of information between said primary storage device and said secondary storage devices by providing read and write signals thereto in response to a predetermined program stored therein, and means responsive to said execution means and said reAd and write signals for arranging and transmitting information in sequential order to said primary storage device so that said information is delivered to destinations determined by said programs in said data handling apparatus.

6. In a data processing system including a shared storage device, a plurality of input-output devices, and means for controlling the passage of information in a plurality of information channels therebetween, a device for establishing priority among said channels comprising a plurality of bistable devices, one for each pair of said channels, means combining indications of the state of said bistable devices, means controlling the state of said bistable devices in response to passage of information through said channels, and means operable in response to combined indications of said bistable devices for establishing priority among said channels.

7. A data processing system adapted to execute a load channel operation in response to an instruction having an operations part and an address part comprising a storage device, an instruction register including means for interpreting instructions and directing corresponding operations, means for storing a program of instructions in said storage device at addresses selectable in a predetermined manner and for reading said stored instructions, a plurality of input-output devices selectable by instruction signals for storing and transmitting data, multi-channel control apparatus adapted to buffer information between said input-output devices and said storage device including operations, address and location registers respectively in each channel and means furnishing signals indicative of said stored information therein, means selecting said input-output devices and said channels of said control apparatus, means reading and transferring said load channel instruction to said instruction register, means operable in response to said instruction register for entering the address part of said load channel instruction plus a predetermined value in said location register of a selected channel and for entering the information from the location specified by said address contained in said load channel instruction in said operations and address registers in said selected channel.

8. A data processing system adapted to execute an input-output control operation in response to an instruction having an operations part, a count, and an address, said system comprising a storage device, an instruction register including means for interpreting instructions and directing corresponding operations, means for storing a program of instructions in said storage device at addresses selectable in a predetermined manner and for reading said stored instructions, a plurality of input-output devices selectable by instruction signals for storing and transmitting data, multi-channel control apparatus adapted to buffer information between said input-output devices and said storage device including means storing operation manifestations, said count, and said addresses of locations in said storage device in each channel and for furnishing signals indicative of said stored information, means selecting said input-output devices and said channels of said control apparatus, means reading and transferring an input-output control instruction from said storage device to a selected channel of said control apparatus, means operable in response to operation manifestations in said operation manifestation means to program the transfer of data in said channel, means operable in response to said count stored in said count storing means to control the quantity of data, and means operable in response to said addresses stored in said address storing means to select the data locations in said storage device.

9. In a data processing system adapted to execute a load channel operation in response to an instruction having an operations part and an address, said system comprising a storage device and an instruction register including means for interpReting instructions and directing corresponding operation, means for storing a program of instructions in said storage device at addresses selectable in a predetermined manner and for reading said stored instructions, a plurality of input-output devices selectable by instruction signals for storing and transmitting data, multi-channel control apparatus adapted to buffer information between said input-output devices and said storage device including means storing operation manifestations and addresses of locations in said storage device in each channel and for furnishing signals indicative of said stored information, means selecting said input-output devices and said channels of said control apparatus, means reading and transferring a load channel instruction from said storage device to said instruction register, means transferring a control instruction at the address specified by said load channel instruction to the selected channel of said control apparatus, means under control of said operation manifestations storing means, operable in response to operation manifestations in said control instruction to program the transfer of data in said channel, means under control of said storing addresses of locations, operable in response to said address in said control instruction to select data locations in said storage device, and means delaying the execution of a second of said load channel instructions when provided until the operation specified by said control instruction is complete.

10. A data processing system comprising a storage device, an instruction register including means for interpreting instructions and directing corresponding operations, means for storing a program of instructions in said storage device at addresses selectable in a predetermined manner and for reading out said stored instructions, a plurality of input-output devices selectable by instruction signals for storing and transmitting data, multi-channel control apparatus adapted to buffer information and to transfer said information between said input-output devices and said storage device and adapted to execute a control instruction having an operation part, a count, and an address including means storing manifestations of said operation, said count, and said addresses in each channel and for furnishing signals indicative of said stored control information, means selecting said input-output devices and said channels of said control apparatus, means reading and transferring said control instruction from said storage device to a selected channel of said control apparatus, and execution means for each channel operable in response to manifestations of said operation part in said operation storing means to control the transfer of data in said channel, operable in response to manifestations of said count to control the quantity of data transferred, and means operable in response to manifestations of said address in said address storing means to select the data locations in said storage device.

11. A data processing system adapted to execute a synchronous load channel operation in response to an instruction having an operations part and an address part comprising a storage device, an instruction register including means for interpreting instructions and directing corresponding operations, means for storing a program of instructions in said storage device at addresses selectable in a predetermined manner and for reading out said stored instructions, a plurality of input-output devices selectable by instruction signals for storing and transmitting data, multi-channel control apparatus adapted to buffer information between said input-output devices and said storage device and controlled by buffer instructions having operations and address parts stored in operations and, address registers respectively in each channel, means furnishing signals indicative of said stored information therein and ready signals when an operation is complete, means selecting said input-output devices and said channels of said control appaRatus, means reading out and transferring said synchronous load channel instruction to said instruction register, and synchronizing means operable in response to said instruction register and said ready signal from said selected channel for entering the buffer instructions from said address in said storage device into said operations and address registers in said selected channel.

12. A data processing system comprising, in combination, an addressable storage device, a primary computer having access to said storage device for instructions and data, a plurality of input-output devices, a plurality of secondary stored program computers and data transmission devices for receiving and transferring data from and to said input-output devices having access to said storage device for receiving instructions and data and for storing data from said input-otuput devices in accordance with said stored programs and means for establishing priority in response to demands for access to said storage device among said primary computer and said plurality of secondary computers, said priority means favoring previous demands and all demands being satisfied in a predetermined period of time.

13. A data processing system comprising, in combination, a computer, an addressable storage device storing data, channel instructions and further instructions including select and control instructions, a plurality of input-output devices, a plurality of control devices having channels coupling said input-output devices to said addressable storage device, means for interpreting said select instructions to render one channel operative to select a chosen input-output device, means interpreting said channel instructions to obtain a control instruction, means controlled by said control instruction for controlling the transfer of data via said selected channel, means controlled by said channel instruction for storing in said selected channel the manifestation of the address of a next control instruction located in said storage means, and means rendered operative upon completion of said transfer of data to render said manifestation of the addresses of a next control instruction effective to select and render operative said next control instruction.

14. A device as in claim 13, and means for establishing priority of access to said storage device between said computer and said channels, and means controlled by the selected channel operation to grant priority of access to said channel instead of to said computer.

15. A device as in claim 13, and including means for establishing priority of access to said storage device, among said channels, means conditioned by operation of a chosen channel, and means controlled by said conditioned means rendering said priority means operative to grant access to said chosen channel, in preference to another channel.

16. In combination, a central processing unit controlled by instruction manifestations and operable upon data manifestations, addressable storage means storing manifestations of data, of instructions and of commands, a plurality of input-output devices for receiving and supplying manifestations of data, a plurality of channels for controlling the flow of data manifestations between said storage means and said input-output devices and including means for storing operation control manifestations, and address manifestations of one kind and of another kind, said commands including operation control manifestations and address manifestations designating addresses of data storage locations in said storage means, and said instruction manifestations including address manifestations designating addresses of commands, means controlled by said central processing unit for extracting a manifestation of instruction from said storage means, for selecting a channel and an input-output device, means controlled by said central processing unit for extracting a manifestation of an instruction for initiating operation of said chosen channel, means controlled by aN address portion of said last named manifestation for storing manifestations in accordance with said address portion in said address manifestation storing means of one kind, and for selecting a command at the designated address in said addressable storage means and relaying said command to said operation control manifestation storage means, and to said address manifestation storage means of said other kind whereby operation of said selected channel is controlled by said operation manifestation storage means to transfer data to or from said selected input-output unit, and from or to said data address respectively, the addresses of data in said storage means being indicated by said address manifestations of said other kind, and means controlled by said address manifestations of said one kind for selecting a command in said storage means, to control further data transfer.

17. A device, as in claim 16, and including means in each channel for storing data quantity manifestations, and said commands including a data quantity manifestation, and means controlled by the address portion of said last named manifestation, relaying said data quantity manifestation to said data quantity manifestation storing means, means operating upon said data quantity manifestation to keep track of the amount of data transferred by altering said manifestation to different statuses and means rendered operative by a certain status to render said means, controlled by said address manifestation of said one kind, effective for selecting another command.

18. A device, as in claim 16, and including means establishing a priority of access to said storage means between said central processing unit and said channels, and means controlling said priority access means to give priority of access to a channel, upon simultaneous demands for access by said central processing unit and said channels.

19. A device, as in claim 16, and including means establishing priority of access to said storage means between two channels, means controlled by operation of said channels to indicate a present state of operation or of non-operation, respectively, of said two channels, and means controlled by said last indicating means for rendering said priority means effective to grant access to said channel indicating a present state of operation.

20. A device, as in claim 16, and including means establishing priority of access to said storage means among a plurality of channels simultaneously requesting access, means conditioned selectively by operation of one channel to establish a claim of priority, and means controlled by first and second, associated units in said one channel, for controlling said conditioned means whereby priority among said channels simultaneously requesting access in given to said second associated unit in said one channel, if said first associated unit was immediately previously operative, but no longer requesting access to said storage means.

21. In combination, a computer, a plurality of input-output devices and a shared addressable storage unit, said unit storing manifestations of data, instructions and commands, each of said instructions including an operation part and an address part and each of said commands including a word count part, an operation designating part and an address part, a plurality of channels connecting said input-output devices and said shared storage unit and each including a data register for receiving data manifestations from said input-output devices to be relayed to said storage unit or data manifestations from said storage unit to be relayed to said input-output units, a location register in each said channel for storing manifestations of said instruction address part, a word counter in each said channel for storing manifestations of said command word count part, an address counter in each said channel for storing manifestation of said command address part, an operation register in each channel for storing said command operations part, means controlled by aN instruction for selecting a channel and selecting an input-output device, means controlled by an address part of an instruction for storing said address part in said location counter, and for selecting a command in said storage unit, means controlled by said last named instruction operation part for transferring said word count part of said selected command to said word address counter, said word address part of said selected command to said word address counter and said operation part of said selected command to said operation register, means for stepping said word counter down and said address counter up, said operation part stored in said operation register, controlling the flow of data to said data register, said flow controlling said word counter, said word address counter designating the storage location of data in said storage unit, and means controlled by said word counter, upon termination of said data transfer, to request access to said storage unit, said address stored in said location register selecting the address of the next command stored in said storage unit.

22. A device, as in claim 21, and including means demanding access to said storage means by said computer and said selected channel and means recognizing both said demands for access, said means granting priority to said channel demand upon simultaneous demand by said computer and said channel.

23. A devive, as in claim 21, and including means recognizing demands for access by a plurality of channels, and means granting priority to said first selected channel, upon a demand emanating from said channel and another channel.

24. Apparatus for providing service in turn to the individual ones of a plurality of devices arranged into a number of groups, each device operable to request service, means establishing service to an individual device, including: means for recognizing which devices request service and which ones have previously been provided service; means for providing priority of service, as among groups of said devices requesting simultaneous service, to the group having the device being presently serviced; and means for providing priority of service, as among devices requesting service in a group, to the device previously serviced.

25. Apparatus for indicating priority of service among a plurality of input line groups carrying signals representative of service requests, including: a number of bi-stable flip-flops, each settable to a selected one of a first and a second state, and each associated with a different group of said input lines; means operative to permit setting to said first state of selected ones of said flip-flops by service signals on any input line in selected ones of said groups; means operative to permit setting to said second state of selected ones of said flip-flops by service signals on any input line in selected ones of said groups associated with selected others of said flip-flops; means operative to maintain the state of any of said flip-flops when service signals attempt to set said flip-flop to said first and second states substantially simultaneously; gating means associated with each flip-flop responsive to the state of a number of others of said flip-flops; and group-priority indicating output means associated with each flip-flop responsive to said associated gating means and operative by the first state of said associated flip-flop.

26. A device as in claim 25 wherein said gating means is responsive to the first state of said associated flip-flops and to the second state of said other flip-flops.

27. A device as in claim 25 wherein each of said group-priority indicating output means is associated with: a number of line-priority indicating output means corresponding to the number of input lines comprising a group, a selected one of said line-priority means corresponding to the input line carrying a service request being operable when said associated group-priority means is operative.

28. In an electronic data processing apparatus, the coMbination comprising a plurality of data utilization devices, each of said devices having a separate demand line to indicate when active the readiness of said device to manipulate data, a control means comprising means for addressing a data storage location for data to be manipulated, an addressable data storage means adapted to have data read therefrom or written thereinto in accordance with addresses derived fon said control means, and a traffic control circuit separately connected to each demand line of said utilization devices and said control means to substantially immediately scan all demand lines connected thereto, bypassing all demand lines which are inactive without response therefrom, until an active demand line is sensed and passing separate control signals to said control means for each active demand line sensed.

29. In combination, a plurality of data manipulating devices, a multiple stage traffic control circuit, a data processor, means including said traffic control circuit repetitively scanning all of said devices and connecting each of said data manipulating devices requiring a data manipulation in sequence to said data processor to perform a single data manipulation, an error signal producing circuit, and electronic switching means under control of said error signal producing circuit connected to said traffic control circuit to interrupt said traffic control circuit in at least one stage upon the occurrence of an error in a data manipulation.

30. In combination, a plurality of data manipulating devices, a multiple stage traffic control circuit, a data processor connected to one stage of said traffic control circuit to be activated thereby, means including said traffic control circuit repetitively scanning all of said devices and connecting each of said data manipulating devices requiring a data manipulation in sequence to said data processor to perform a single data manipulation, an error signal producing circuit, an electronic switching means under control of said error signal producing circuit connected to said traffic control circuit to interrupt said traffic control circuit in at least one stage upon the occurrence of an error in a data manipulation.

31. A data manipulating apparatus comprising data supply means having a plurality of data items therein each arranged as a plurality of data words, and an end-of-item indicator separating the respective items, a memory unit having a plurality of separately addressable storage locations to which all of said data is to be transferred, a memory address selector, control means adapted to store address data defining an address in said memory unit, means including said control means activated by each incoming data word to transfer directly the data word unmodified to an address location specified by said address data from said control means, means including said control means modifying the address defining data each time said address data is used, an end-of-item indicator sensing means, and means including said end-of-item sensing means connected to effect modification of the address data in said control means.

32. A data manipulating apparatus comprising data supply means having a plurality of data items therein each arranged as a plurality of data words, and an end-of-item indicator separating the respective items, a memory unit having a plurality of separately addressable storage locations to which all of said data is to be transferred, a memory address selector, control means adapted to store address data defining an address in said memory unit, means including said control means activated by each incoming data word to transfer directly the data word unmodified to an address location specified by said address data from said control means, means including said control means modifying the address defining data each time said address data is used, an end-of-item indicator sensing means, and means including said end-of-item sensing means connected to effect modification of the address data in said Control means, said last-named means comprising memory output sensing means connected to said memory address selector and to said control means.

33. A data manipulating apparatus comprising data supply means having a plurality of data items therein each arranged as a plurality of data words, and an end-of-item indicator separating the respective items, a memory unit having a plurality of separately addressable storage locations to which all of said data is to be transferred, a memory address selector, control means adapted to store address data defining an address in said memory unit, means including said control means activated by each incoming data word to transfer directly the data word unmodified to an address location specified by said address data from said control means, means including said control means modifying the address defining data each time said address data is used, an end-of-item indicator sensing means, and means including said end-of-item sensing means connected to effect modification of the address data in said control means, said last-named means comprising memory output sensing means connected to said memory address selector and to said control means, said control means modifying the data received from said memory output sensing means.

34. Apparatus for arranging a plurality of data words in an addressable main memory comprising a control memory having a plurality of addressable storage positions, a control memory address selector, means connected to said control memory address selector to set a predetermined address therein indicative of an incoming word, a main memory address selector, means including said control memory address selector reading an address for said main memory from said predetermined address in said control memory into said main memory address selector to select a location in said main memory for said incoming word, and means connected to said control memory to modify the main memory address from said predetermined address in said control memory and reinsert said modified main memory address at said predetermined address in said control memory.

35. Apparatus for transferring a plurality of data words relative to an addressable main memory comprising a control memory having a plurality of addressable storage positions, a control memory address selector, means connected to said control memory address selector to set a predetermined address therein indicative of the need for a data word to be transferred, a main memory address selector, means including said control memory address selector reading an address for said main memory from said control memory into said main memory address selector to select a location for said data word which is to be transferred, and means connected to said control memory to modify the main memory address from said predetermined address in said control memory and reinsert said modified main memory address at said predetermined address in said control memory.

36. Apparatus for transferring a plurality of data words relative to an addressable main memory comprising a control memory having a plurality of addressable storage positions, a control memory address selector, means connected to said control memory address selector to set a predetermined address therein indicative of the need of a word to be transferred, a main memory address selector, means including said control memory address selector reading an address for said main memory from said control memory into said main memory address selector to select a location for said word which is to be transferred, means connected to said control memory to modify the main memory address from said control memory and reinsert said modified main memory address at said predetermined address in said control memory, and means connected to said control memory to effect a transfer from said main memory of substitute control data for insertion in said predetermined address in said control memory.

37. In a data processing apparatus, the combination comprisinG a main memory, said memory being adapted to store data words each at a separately addressable location, a main memory address selector for selecting the address for each data word in said main memory, a control memory having a plurality of addressable storage locations, said control memory being adapted to store control data for said main memory, a control memory address selector, a data transfer circuit, indicating means connected to said last-named circuit to indicate said transfer circuit is conditioned to transfer a data word, means including said indicating means setting an address in said control memory address selector, control memory activating means connected to said control memory to read control data therefrom at a selected address location into said main memory address selector, means including said main memory address selector effecting a direct transfer of data without modification between said transfer circuit and said main memory, and means connected to said control memory to modify the control data read into said main memory address selector.

38. Apparatus for arranging a plurality of data words in an addressable main memory comprising a control memory having addressable storage locations, a control memory address selector, means connected to said control memory address selector to set a first predetermined address therein indicative of a word to be transferred, a main memory address selector, means including said control memory address selector reading an address from said control memory into said main memory address selector to select a location in said main memory for said incoming word, means connected to said control memory to modify the main memory address from said control memory and reinsert said modified main memory address at said predetermined address, word sensing means connected to said main memory to sense the contents of each word transferred, said word sensing means being connected to said control memory address selector to set a second predetermined address therein so that a special address in said main memory will be selected and data at said special address will be inserted into said first predetermined address in said control memory.

39. In a data processing apparatus, the combination comprising a main memory, said memory being adapted to store data words at separately addressable storage locations, a main memory address selector for selecting the address for each data word in said main memory, a control memory having a plurality of addressable storage locations, said control memory being adapted to store control data for said main memory, a control memory address selector, a data transfer circuit, indicating means connected to said last-named circuit to indicate said transfer circuit is conditioned to transfer a data word, means including said indicating means setting a first address in said control memory address selector, control memory activating means connected to said control memory to read control data therefrom into said main memory address selector, means including said main memory address selector effecting a transfer of data between said transfer circuit and said main memory, means connected to aid control memory to modify the control data read into said main memory address selector, selective data sensing means connected to said data transfer circuit, means connecting said data sensing means to said control memory address selector to set a second address therein, and means including said data sensing means effecting a change of the data in said control memory at said first address.

40. Apparatus for arranging a plurality of data words in an addressable main memory comprising a control memory having a plurality of addressable storage locations, a control memory address selector, means connected to said control memory address selector to set a predetermined address therein indicative of a word to be transferred, a main memory address selector, means including said control memory address selector reading a first address froM said control memory into said main memory address selector to select a location for said incoming word, and means connected to said control memory to modify by unity the main memory address from said control memory and reinsert said modified main memory address at said predetermined address in said control memory.

41. In a data processing apparatus, the combination comprising a plurality of data utilization devices, each of said devices being adapted to receive and transmit data, a programmed data processor, a traffic control circuit, demand indicating lines connected from each of said utilization devices to said traffic control circuit, electronic switching means connected to said traffic control circuit to scan substantially immediately all of the demand lines until an active demand line is sensed. said switching means being adapted to lock directly onto only those demand lines in a selected sequence which are active and bypassing without response therefrom those demand lines which are inactive, data storage means, and control means comprising data selecting means connected to be controlled by each utilization device whose demand line is active, said control means being connected to effect a data transfer with respect to said data storage means in accordance with the device in demand.

42. In combination, in a data processing apparatus, a first data manipulation traffic control adapted to scan a plurality of operation demand lines and initiate a control signal and thereby a data manipulation only with respect to each active demand line which is calling for operation, a second data manipulation traffic control adapted to scan a plurality of operation active demand lines and initiate a control signal and thereby a data manipulation only with respect to each active demand line which is calling for operation, a data processor connector to receive control signals from said first and second traffic controls to initiate a control action in said data processor related to a selection made by said second traffic control.

43. In combination, in a data processing apparatus, a first data manipulation traffic control adapted to scan a plurality of operation demand lines and initiate a control signal and thereby a data manipulation only with respect to each active demand line which is calling for operation, a second data manipulation traffic control adapted to scan a plurality of operation demand lines and initiate a control signal and thereby a data manipulation only with respect to each active demand line which is calling for operation, a data processor connector to receive control signals from said first and second traffic controls to initiate a control action in said data processor related to a selection made by said second traffic control, and means to step said second traffic control after a predetermined operation of said data processor when under the control of said second traffic control.

44. In combination, in a data processing apparatus, a first data manipulation traffic control adapted to scan a plurality of operation demand lines and initiate a control signal and thereby a data manipulation only with respect to each active demand line which is calling for operation, a second data manipulation traffic control adapted to sense a plurality of operation demand lines and initiate a control signal and thereby a data manipulation only with respect to each active demand line which is calling for operation, a data processor connected to receive transfer control signals from said first traffic control and data manipulation program orders from said second traffic control to initiate a control action in said data processor related to a selection made by said second traffic control.

45. In combination with a data processor, a plurality of peripheral data handling devices said devices each being adapted to have an output operational demand signal which is active when said device is ready to operate, an operational traffic control having a plurality of coNtrol stations, each station of which is connected to one each of said peripheral devices to sense only the active operational demand signals produced by said devices and to bypass without response therefrom those devices having no operational demand signal, a traffic control signal source comprising an electronic switching means connected to said traffic control to step said traffic control from one active demand signal to the next so that each device receives at least one operational control impulse for a predetermined data manipulation after which the traffic control steps substantially immediately to the next active demand signal, and a control circuit connected to be controlled by the output from said traffic control.

46. In combination with a data processor, a plurality of peripheral data handling devices each of said devices having an input buffer and an output buffer, and the buffers of said devices each being adapted to have an output operational demand signal which is active when the associated buffer is ready to operate, an operational traffic control having a plurality of control stations each independently connected to one each of said buffers to sense active operational demand signals produced by said buffers and to bypass without response therefrom any buffer not having an active operational demand signal, a traffic control signal source connected to said traffic control to step said traffic control from one active operational demand signal to the next so that each buffer receives at least one operational control impulse for a predetermined data manipulation after which the traffic control steps substantially immediately to the next active demand line, and a control circuit connected to be controlled by the output from said traffic control.

47. In a data processing apparatus, the combination comprising a plurality of data utilization devices, each of said devices being adapted to receive and transmit data, a programmed data processor, a traffic control circuit, demand indicating lines connected from each of said utilization devices to said traffic control circuit, electronic switching means connected to said traffic control circuit to scan substantially immediately all of the demand lines, bypassing without response therefrom the inactive demand lines, until an active demand line is sensed, data storage means, control means comprising data selecting means connected to be controlled by each utilization device whose demand line is active, said control means being connected to effect a data transfer with respect to said data storage means in accordance with the device in demand, and clock means producing a traffic control signal connected to said signal means to switch said traffic control circuit from one active demand indicating line to the next active demand indicating line.

48. An on-line data processing system for processing call requests from keysets and the like comprising a central processing portion, said central processing portion including a computer means and means for receiving said call requests, a plurality of peripheral units, each of said peripheral units including information storage means and control register means, said central processing portion also including means responsive to a received call request for directing to said control register means data for controlling the transfer of information between said information storage means and said central processing portion, and transfer means for each of said peripheral units, said transfer means being controlled by said control data to carry out the transfer of information between the corresponding one of said peripheral units and said central processing portion.

49. A data processing system as set forth in claim 48, including means at said peripheral units to develop a BID signal indicating that the corresponding peripheral unit is conditioned for a transfer of information, and means at said central processing portion responsive to said BID siGnal for inhibiting the operation of said computer means to permit said transfer to take place.

50. A data processing system as set forth in claim 49 further including priority selector means for enabling a predetermined one of said transfer means in accordance with a predetermined priority schedule.

51. In an on-line data processing system for processing call requests comprising a central processor portion including data storage means, computer means operable upon data stored in said data storage means, and means for receiving said call requests and for directing corresponding data signals to said data storage means to be operated on by said computer means; a plurality of peripheral units for storing inventory information to be processed in accordance with said call requests each of said peripheral units including control register means, said computer means being operative in accordance with said call requests to load instructional data in a selected one of said control register means, said peripheral units further including transfer means responsive to said control register means in accordance with said instructional data for identifying particular inventory information and for effecting a transfer thereof between said data storage means and said inventory storage means.

52. A data processing system as set forth in claim 51 wherein said transfer means further includes synchronizing register means for temporarily storing said identified information.

53. In an on-line data processing system, a central processor portion, a plurality of periheral units each including inventory storage means and control register means, said central processor portion including a computer section and data storage means operable with said computer section, a plurality of keysets for initiating call requests and for directing said call requests to said central processor portion, means included at said central processor portion for receiving said call requests and for transmitting transfer instructional data to a selected one of said control register means corresponding to identifying signals contained in the call request, said control register means including means for addressing said data storage means and said inventory storage means and means for establishing the operational state of said peripheral unit, and synchronizing register means for receiving digits of inventory information to be transferred between a selected peripheral unit and said data storage means.

54. Data processing system as set forth in claim 53, including signal means at each peripheral unit for generating a BID signal when that peripheral unit is conditioned to effect a transfer of inventory information, priority selector means responsive to said BID signals so generated for developing an ALLOW signal individual to one of said peripheral units according to a preset priority schedule, and means at said peripheral units responsive to the ALLOW signal to carry out the selected data transfer.

55. A data processing system as set forth in claim 54, including inhibiting means at said central processor, said inhibiting means being responsive to a BID signal and operative thereby to prevent further operations of said computer section until the data transfer has been effected.

56. An on-line data processing system comprising a central processor portion and a plurality of peripheral units arranged for operation with said central processor portion, said central processor portion including data storage means and program control means having a plurality of preset programs, means for directing call requests to said central processor portion on a random basis, said central processor portion including means for receiving said call requests on a one-at-a-time basis, control register means at said peripheral units arranged to receive instructional data defining a particular data transfer operatIon between the peripheral unit and said data storage means, said central processor portion including means responsive to signals of a call request for transmitting to said control register means a particular preset program corresponding to said signals of the call request, synchronizing register means for storing the information to be transferred on a bit basis, means operative upon said peripheral unit being conditioned to effect a transfer of a bit of inventory information for providing a BID signal, access providing means responsive to a BID signal for selectively providing communication between one of said peripheral units and said central processor portion according to a predetermined priority schedule, and means included in said control register means for addressing said data storage means upon access being provided to said one peripheral unit for transferring said bit of inventory information.

57. An on-line data processing system for processing call requests comprising a central processing portion and a plurality of peripheral units, said central processor portion including data storage means and program means for containing a plurality of sets of instructional data to be selectively transmitted to a selected one of said peripheral units in response to identifying signals forming part of each request, each of said peripheral units including inventory storage means and control register means to receive said selected instructional data for independently controlling the transfer of inventory information between said data storage means and said inventory storage means, synchronizing register means for temporarily storing said inventory information to be transferred, means for indicating the conditioning of said temporary storing means for the transfer of inventory information, means responsive to said indicating means for selectively providing communication between said one peripheral unit and said central processor portion according to a predetermined priority schedule, means included in said control register means for addressing said data storage means upon communication being provided to said one peripheral unit, and means for transferring said inventory information between said temporary storing means and said data storage means as addressed by said addressing means.

58. An on-line data processing system for processing call requests including a central processor portion having input/output storage means and a plurality of peripheral units, each of said peripheral units including inventory storage means and means for effecting a transfer of inventory information between the inventory storage means and said input/output storage means, said transfer means including individual programming means for said peripheral unit; said programming means including control register means having state register means operative for determining the operational state of said peripheral unit, inventory register means for addressing said inventory storage means, and processor register means for addressing said input/output storage means; means forming part of said central processor portion for directing to said control register means program instructions developed in accordance with signals contained in a received call request; synchronizing register means for effecting the transfer of data between said inventory storage means and said input/output storage means, and means responsive to said synchronizing register means for determining preferential communication between a particular one of said peripheral units and said central processor portion.

59. A data processing system as set forth in claim 58 further including means for modifying the instructional data in said inventory register means and said processor register means upon each transfer of data between said input/output storage means and said inventory storage means.

60. An on-line data processing systeM for processing call requests comprising means for receiving said call requests on a random basis, a central processor portion including a data storage means and program control means, a plurality of peripheral units each having control register means and inventory storage means, said program control means having a plurality of preset programs and operative upon the receipt of a call request to transmit a particular one of said preset programs to said control register means, addressing means forming part of said control register means for defining a block of information addresses of said inventory storage means and for defining a block of information addresses of said data storage means, each of said peripheral units including synchronizing register means for receiving inventory information to be transferred between said data storage means and said inventory storage means, each of said peripheral units further including means for generating a signal indicative of a transfer condition therefor, and means responsive to said signals so generated for transferring said inventory information on a preferential basis between a selected one of said synchronizing register means and said data storage means of said central processor portion.

61. An on-line data processing system including a central processor portion and a plurality of peripheral units and means for transferring information between individual ones of said peripheral units and said central processor portion, said transferring means including a priority selector device and circuit means responsive to said priority selector device for interconnecting said central processor portion and said peripheral units, said priority selector device being responsive to said peripheral units being in a transfer condition and operative to provide access through said circuit means between a selected one of said peripheral units and said central processor portion according to a predetermined priority schedule, said peripheral units including individual programming means for controlling the transfer of information between said particular one of said perhipheral units and said central processor portion through said circuit means.

62. A data processing system as in claim 61 wherein said central processor portion and said peripheral units each include storage means between which information is to be transferred, said individual programming means each including first means for addressing said storage means of said central processor portion and second means for addressing said storage means of said peripheral unit.

63. A data processing system as in claim 62 wherein each of said first and second means is a working storage register adapted to be decremented upon each addressing operation thereby.

64. A data processing system as in claim 61, wherein said priority selector device comprises a plurality of input terminals each coupled to one of said peripheral units to receive a BID signal therefrom, a plurality of output terminals each corresponding to one of said peripheral units an interconnecting circuit between each input terminal and the corresponding output terminal, said interconnecting circuits including gate means operable, in response to a higher-priority BID signal, to inhibit the development of an output signal on its output terminal.

65. An on-line data processing system for inventory control purposes comprising a central processing portion including a computer section and an addressable data storage means, a plurality of randomly operative keysets for originating any of a number of call requests, a plurality of peripheral units including means for maintaining current records of inventory information to be processed in response to said radomly received call requests, said central processing portion including means for individually programming selected ones of said peripheral units in accordance with a Received call request, each of said peripheral units including control register means for storing said programs and means for temporarily storing information to be transferred to and from said central processing portion, means responsive to the storage state of said temporary storing means for seeking access to said central processing portion, means responsive to said access seeking means for determining preferential access for a particular peripheral unit according to a priority schedule, first means responsive to said determining means for transferring inventory information between said temporary storing means of a preferred peripheral unit and said central processor, and means for inhibiting said computer section of said central processing portion during a transfer of said inventory information.

66. In an on-line data processing system comprising a central processor portion and a plurality of peripheral units, each of said plurality of peripheral units including control register means and inventory storage means for inventory statistics, a plurality of keysets, said central processor portion being responsive to said keysets on a random basis for transmitting predetermined program instructions to said control register means, said register means being operative thereby to address said inventory storage means, temporary storage means, first means responsive to said control register means for transferring said inventory statistics on a bit basis between said inventory storage means and said temporary storage means, and second means for controlling the transfer of said bits of said inventory statistics on a preferential basis between said temporary storage means of said perhipheral units and said central processor portion.

67. A data processing system as claimed in claim 66, wherein said control register means includes a register stage for indicating the number of data transfer operations to be carried out, and means responsive to said register stage for stopping further transfer operations after the required number have been completed.

68. In an on-line data processing system, a central processor portion including means for storing a plurality of preset programs and for receiving a plurality of call requests on a random basis, a plurality of peripheral equipments associated with said central processor portion said processor portion being operative in response to an individual call request to direct a predetermined one of said preset programs to a particular one of said peripheral equipments, said peripheral equipments each including control register means for receiving said predetermined program, storage means included in each of said peripheral units, said control register means further including means for storing instructions representing a present address of said storage means, means responsive to said control register means for addressing said storage means, and means for decrementing said stored address instructions upon each addressing of said storage means.

69. In an on-line data processing system comprising, a central processor portion including data storage means addressable on a random basis, a plurality of peripheral units associated with said central processor portion, each of said peripheral units including inventory storage means and control register means for independently controlling the operation thereof, said control register means including means to receive from said central processor portion program instructions developed in accordance with a received call request, said control register means including first means for addressing said data storage means and second means for addressing said inventory storage means, means responsive to said control register means for transferring inventory statistics between said inventory storage means and said data storage means, said transfer means inclUding means operative to modify said control register first and second means upon a transfer being effected whereby the next address of said inventory storage means of said peripheral unit is identified and the next address of said storage means of said central processor portion is identified.

70. An on-line data processing system comprising a central processor portion and a plurality of peripheral units, said central processor portion comprising computer means and randomly accessible first storage means adapted as an input/output device for said computer means, said peripheral units each including a control register means and a second storage means for storing inventory statistics and the like, said central processor portion also including means for developing instructional data for effecting the operation of any one of said control register means in accordance with the specific nature of a call request, said control register means including means for addressing said first and said second storage means in accordance with said instruction data, and means responsive to said control register means for effecting a transfer of information between said first and second storage means.

71. A data processing system as set forth in claim 70 including means for interrupting the operation of said computer means concurrently with the operation of said transfer effecting means.

72. A data processing system as set forth in claim 71, including means for controlling the operation of said transfer effecting means on a predetermined priority schedule.

73. An on-line data processing system comprising a central processor portion for processing inventory statistics in accordance with a received call request, said processor portion including computer means having an addressable input/output storage means, a plurality of peripheral units for storing inventory statistics to be processed by said computer means and including inventory storage means, control register means for each of said peripheral units and adapted to be selectively instructed by said central processor portion in accordance with a received call request; said control register means including first register means for establishing the operational state of said peripheral unit, second register means defining one address of a group of addresses of said inventory storage means, and third register means for defining one address of a group of addresses of said input/output storage means; means controlled by said first register means in accordance with said operational state for effecting a transfer of inventory statistics on a bit basis between consecutive corresponding addresses of said inventory storage means and said input/output storage means; means operative to modify the instructions contained in said second and third register means upon each addressing of said inventory storage means and said input/output storage means respectively; and means for controlling the operation of said transfer effecting means on a preferential basis according to a priority schedule.

74. A data processing system as set forth in claim 73 wherein means are included in said control register means for interconnecting said first, second and third registers in a register arrangement.

75. In a data processing system having a central processor portion and a plurality of peripheral units to be provided preferential access to said central processor portion, each of said peripheral units including means for generating a BID signal, priority selector means having a plurality of input terminals each assigned a lower order of priority than the preceding input terminal, a corresponding plurality of output terminals, each of said input terminals being connected to a predetermined one of said BID signal generating means, said selector means including logic means interconnecting each input terminal to a corresponding output terminal, each of said logic means including an inhibit terminal connected to the input terminals of higher assigned priority, said output terminals being operative to provide communication between the corresponding one of said peripheral units and said central processor portion.

76. A data processing system comprising a plurality of peripheral data transmitting and receiving devices, a plurality of channels each adapted to establish an operative relationship with respective ones of said peripheral devices, a memory subsystem having a unique cell reserved for each of said channels, said cell containing the indirect address of a memory buffer area, a general purpose arithmetic subsystem for performing computation upon binary coded data and for receiving both arithmetic and input/output commands from said memory subsystem, said arithmetic subsystem including means for distinguishing an input/output command and initiating a data exchange between a selected peripheral device and the memory buffer area associated with its channel, and means responsive to a predetermined command word for providing an operational mode providing a continuous data exchange between a selected peripheral device and memory buffer area independent of said arithmetic subsystem.

77. The data processing system defined in claim 76 comprising means for inhibiting data transfers between said peripheral devices and said memory subsystem during said operational mode, said means being independent of said airthmetic subsystem.

78. The data processing system defined in claim 76 comprising means for regulating the flow of data between said memory subsystem and said peripheral data transmitting and receiving devices so that the devices having the highest data rates are automatically afforded the highest priority use of said memory subsystem.

79. In a data processing system, the combination of: a plurality of peripheral data transmitting and receiving devices, a plurality of channels each adapted to establish an operative relationship with respective ones of said peripheral devices, a memory subsystem having a unique cell reserved for each of said channels, and means operating in conjunction with said channels and said memory subsystem for providing an operational mode wherein one or more of said peripheral devices may continuously exchange data with a selected memory area.

80. In the data processing system defined in claim 79, means for generating a binary encoded code corresponding to each channel for automatically generating the address of said reserved cell.

81. In the data processing system defined in claim 79, means for regulating the flow of data between said memory and said peripheral data transmitting and receiving devices so that the devices having the highest data rates are automatically afforded the highest priority use of said memory.

82. In the data processing system defined in claim 79, a general purpose arithmetic subsystem for performing computation upon binary coded data and for receiving both arithmetic and input/output commands from said memory, said arithmetic subsystem including means for distinguishing an input/output command and subsequently transferring said command to one of said channels after which said arithmetic subsystem is free for performing arithmetic computations and receiving subsequent commands from said memory.

83. In a computer system, a processor capable of processing data in a plurality of cycles, said processor including a randomly accessible memory capable of being selectively chosen for access by said processor in any one or more of said cycles, said processor including means operable in each cycle to provide a processor request signal indicating whether or not the processor requires access to the memory during the next cycle, said processor also including timing means for initiating a processor cycle and for providing timing signalS during each initiated processor cycle, at least one peripheral unit including means for providing a peripheral request signal requesting access to said memory, said peripheral unit being capable of randomly accessing said memory independently of said processor to permit data to be transferred therebetween, the period of a cycle of said processor being relatively small with respect to the period between transfers of data by said peripheral unit, first control means coupled to said timing means and responsive to said processor and peripheral request signals for inhibiting generation of a new processor cycle when both said processor and said peripheral unit request use of the memory for the same period, and second control means for initiating access of said memory by said peripheral unit in response to a request for same whenever said processor is not making use of said memory.

84. In a computer system, a processor capable of processing data in a plurality of cycles, said processor including a randomly accessible memory capable of being selectively chosen for access by said processor in any one or more of said cycles, said processor including means operable in each cycle to provide a processor request signal indicating whether or not the processor requires access to the memory during the next cycle, said processor also including timing means for initiating a processor cycle and for providing timing signals during each initiated processor cycle, at least first and second peripheral units each including means for providing a peripheral request signal requesting access to said memory, each peripheral unit being capable of randomly accessing said memory independently of one another and of said processor, the period of a cycle of said processor being relatively small with respect to the period between transfers of data by a peripheral unit, first control means coupled to said timing means and responsive to said processor and peripheral request signals for inhibiting generation of a new processor cycle when said processor and at least one peripheral unit request use of the memory for the same period, second control means for giving one peripheral unit priority over the other for access to said memory, third control means for initiating access of said memory by a peripheral unit whenever said processor or the other peripheral unit is not making use of same, and means cooperating with said first control means for permitting generation of a new processor cycle after access of said memory by a peripheral unit.

85. In a computer system, a processor capable of processing data in a plurality of cycles, said processor including a randomly accessible memory capable of being selectively chosen for access by said processor in any one or more of said cycles, said processor including means operable in each cycle to provide a processor request signal indicating whether or not the processor requires access to the memory during the next cycle, a processor address register and a processor input-output register cooperating with said memory to permit access of a selected address in said memory in accordance with said processor address register, at least one peripheral unit including means for providing a peripheral request signal requesting access to said memory, said peripheral unit also including a peripheral address register and a peripheral input-output register capable of cooperating with said memory in the same manner as said processor address register and said processor input-output register, the period of a cycle of said processor being relatively small with respect to the period between transfers of data by said peripheral unit, means for gating said registers so as to permit either the processor or said peripheral unit to access said memory independently of one another, first control means responsive to said processor and peripheral request signals for inhibiting genEration of a new processor cycle when both said processor and said peripheral unit request use of the memory for the same period, and second control means for initiating access of said memory by said peripheral unit in response to a request for same whenever said processor is not making use of said memory.

86. In a computer system, a processor capable of processing data in a plurality of cycles, said processor including a randomly accessible memory capable of being selectively chosen for access by said processor in any one or more of said cycles, said processor including means operable in each cycle to provide a processor request signal indicating whether or not the processor requires access to the memory during the next cycle, said processor including processor memory access indicating means for indicating when the processor is using the memory and processor memory request indicating means for indicating whether the processor requests access to the memory during the next processor cycle, at least one peripheral unit including peripheral request indicating means for indicating when said peripheral unit requests access to said memory, the period of a cycle of said processor being relatively small with respect to the period between transfers of data by said peripheral unit, means coupled to said processor memory request indicating means and said peripheral request indicating means for inhibiting generation of a new processor cycle when both said processor and said peripheral unit request access to the memory for the same period, and means coupled to said peripheral request indicating means and said processor memory access indicating means for permitting said peripheral unit to access said memory independently of said processor when said processor is not accessing the memory.

87. In a computer system, a processor capable of processing data in a plurality of cycles, said processor including timing means for initiating a processor cycle and for providing timing control signals during each initiated processor cycle, said processor also including a randomly accessible memory capable of being selectively chosen for access by said processor in any one or more of said cycles, said processor including means operable in each cycle to provide a processor request signal indicating whether or not the processor requires access to the memory during the next cycle, means including processor address means and processor input-output means for cooperating with said memory to permit performance of a memory cycle during which a selected address in memory is accessed in accordance with said processor address means, said processor further including processor memory access indicating means for indicating when the processor is using the memory and processor memory request indicating means for indicating whether the processor requests access to the memory during the next processor cycle, at least one peripheral unit including peripheral address means and peripheral input-output means capable of cooperating with said memory in the same manner as said processor address means and said processor input-output means, the period of a cycle of said processor being relatively small with respect to the period between transfers of data by said peripheral unit, gating means for gating said address means and said input-output means so as to permit either the processor address and input-output means or the peripheral address and input-output means to access said memory independently of one another, said peripheral unit also including a peripheral request indicating means for indicating when said peripheral unit requests access to said memory, means coupled to said processor memory request indicating means and said peripheral request indicating means for inihibiting generation of a new processor cycle when both said processor and said peripheral unit request access to the memory for the same period, and means coupled to said peripheral request indicating means and said processor memory access indicating means for permitting said peripheral unit to access said memory via said gating means when said processor is not accessing the memory.

88. In a computer system, a processor capable of processing data in a plurality of cycles, said processor including a randomly accessible memory capable of being selectively chosen for access by said processor in any one or more of said cycles, said processor including means operable in each cycle to provide a processor request signal indicating whether or not the processor requires access to the memory during the next cycle, means cooperating with said memory to provide access thereto in discrete memory cycles each of duration of the same order as a processor cycle, first indicating means for indicating when said processor is accessing said memory during a processor cycle, second processor indicating means for indicating when the next cycle of said processor requires access of said memory, at least one peripheral unit including means for accessing said memory independently of said processor, said peripheral unit also including peripheral request indicating means, means coupled to said first processor indicating means and said peripheral request indicating means for permitting said peripheral to access said memory independently of said processor when said processor is not accessing the memory, the period of a cycle of said processor being relatively small with respect to the period between transfers of data by said peripheral unit, and means coupled to the first and second processor indicating means and said peripheral request indicating means for inhibiting the performance of the next cycle by said processor when both said processor and said peripheral unit request access to the memory for the same period, the next processor cycle being inhibited until the peripheral unit completes a memory cycle.

89. For use with a data processing system comprising, in combination, a computer, an addressable storage device storing data, channel instructions and further instructions including select and control instructions, and a plurality of input/output devices, a control device comprising: channels coupling said input/output devices to said addressable storage device, means for interpreting said select instructions to render one channel operative to select a chosen input/output device, means interpreting said channel instructions to obtain a control instruction, means controlled by said control instruction for controlling the transfer of data via said selected channel, means controlled by said channel instruction for storing in said selected channel the manifestation of the address of a next control instruction located in said storage means, and means rendered operative upon completion of said transfer of data to render said manifestation of the address of a next control instruction effective to select and render operative said next control instruction.

90. A control device as in claim 89 including means for establishing priority of access to said storage device between said computer and said channels, and means controlled by the selected channel operation to grant priority of access to said channel instead of to said computer.

91. A control device as in claim 89 including means for establishing priority of access to said storage device, among said channels, means conditioned by operation of a chosen channel, and means controlled by said conditioned means rendering said priority means operative to grant access to said chosen channel, in preference to another channel.

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